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Your search returned 22 records. Click on the hyperlinks to view further details of Titles.. |
Magazine Name : Ieee Journal Of Solid-State Circuits
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Year : 2002 Volume number : 37 Issue: 11 |
Jitter Optimization Based On Phase-Locked Loop Design Parameters
(Article)
Subject:
Jitter
,
Phase Noise
Author:
Mozhgan
Mansuri
C. K
Yang
page:
1375
-
1382
Methodology And Experimentral Verification For Substrate Noise Reduction In Cmos Mixed-Signal Ics With Synchronous Digital Circuits
(Article)
Subject:
Crosstalk
,
Integrated Circuit Modeling
Author:
Mustafa
Badaroglu
Marc Van
Heijningen
page:
1383
-
1395
Adaptive Body Bias For Reducting Impacts Of Die-To Die And Within-Die Parameter Variations On Microprocessor Frequency Adn Leakage
(Article)
Subject:
Body Bias
,
Microprocessors
Author:
James W.
Tschanz
Jaems T
Kao
page:
1396
-
1402
Adaptive Supply Serial Links With Sub-I-V Operation And Per-Pin Clock Recovery
(Article)
Subject:
Adaptive Power-Supply Regulation
Author:
M A
Horowitz
J.
Kim
page:
1403
-
1413
A Low-Power Small-Area =7.28-Ps Jitter 1-Ghz Dll-Based Clock Generator
(Article)
Subject:
Clock Generator
,
Delay-Locked Loop
Author:
Chulwoo
Kim
In-Chul
Hwang
page:
1414
-
1420
5-Ghz 32-Bit Integer Execution Core In 130-Nm Dual-Vt Cmos
(Article)
Subject:
Cmos Integrated Circuit
,
Integrated Circuit Design
Author:
Sriram
Vangal
Mark A
Anders
page:
1421
-
1432
A Fully Bypassed Six-Issue Integer Datapath Adn Register File In The Itanium-2 Microprocessor
(Article)
Subject:
Digital Intergated Circuits
,
Microprocessor
Author:
Eric S
Fetzer
Mark
Gibson
page:
1433
-
1440
The Implementation Of The Itaium 2 Microprocessor
(Article)
Subject:
Computer Architecture
,
Microprocessor
Author:
Glenn
Colon-Bonet
Samuel D
Naffzier
page:
1448
-
1460
Implementation Of A Third-Generation 1.1 Ghz 64-Bit Microprocessor
(Article)
Subject:
Integrated Circuit Design
,
Logic Design
Author:
Georgios K
Konstadinidis
Kevin
Normoyle
page:
1461
-
1469
A 0.25-Um 3.0-V Itic 32-Mb Nonvolatile Ferroelectric Ram With Address Transition Detector And Current Forcing Latch Sense Amplifier Scheme
(Article)
Subject:
Nonvolatile
,
Ferroelectric Random Access Momory
Author:
M
Choi
Byung-Gil
Jeon
page:
1472
-
1478
A Quasi-Matrix Ferroelectric Memory For Future Silicon Storage
(Article)
Subject:
Ferroelectric
,
Ferroelectric Memories
Author:
Toshiyuki
Nishihara
Yasuyuki
Ito
page:
1479
-
1484
A 44-Mm Four-Bank Eight-Word Page-Read 64-Mb Flash Memory With Flexible Block Redundancy And Fast Accurate Word-Line Voltage Controller
(Article)
Subject:
Dual Operation
,
Flash Memories
Author:
Toru
Tanzawa
Akira
Umezawa
page:
1485
-
1492
A 125-Mm 1-Gb Nand Flash Memory With 10-Mbyte/S Progam Speed
(Article)
Subject:
Flash Memories
,
High Speed Programming
Author:
Kenichi
Imamiiya
Hiroshi
Nakamura
page:
1493
-
1501
High-Performance 1-Gb Nand Flash Memory With 0.12-Um Technology
(Article)
Subject:
Cashe Progam
Author:
J
Lee
Heung-Soo
Im
page:
1502
-
1509
Memory Design Using A One-Transistor Cain Cell On Soi
(Article)
Subject:
Capacitor-Less
,
Gain Cell
Author:
Katsuyuki
Fujita
Takashi
Ohsawa
page:
1510
-
1522
The On-Chip 3-Mb Subarray-Based Third-Level Cashe On An Itanium Microprocessor
(Article)
Subject:
Cache Memories
,
Memory
Author:
Don
Weiss
John J
Wuu
page:
1523
-
1529
A 600-Mhz Vliw Dsp
(Article)
Subject:
Digital Signal Processing
,
Signal Integrity
Author:
Sanjive
Agarwala
Timothy
Anderson
page:
1532
-
1544
A 175-Mv Multiply-Accumulate Unit Using An Adaptive Supply Voltage And Body Bias Architecture
(Article)
Subject:
Active Power
,
Adaptive Body
Author:
Jaems T
Kao
Masayuki
Miyazaki
page:
1545
-
1554
A Unified Turbo/Viterbi Channel Decoder For 3gpp Mobile Wirelwss In 0.18-Um Cmos
(Article)
Subject:
Channel Decoding
,
Mobile Communication
Author:
Mark A
Bickerstaff
David
Garrett
page:
1555
-
1564
10-And 40-Gb-S Forward Error Correction Devices For Optical Communications
(Article)
Subject:
Forward Error Correction
,
Optical Communication
Author:
L
Song
M
Yu
page:
1565
-
1573
A 27-Mhz-54-Mhz 11-Mw Mpeg-4 Video Decoder Lsi For Mobile Applications
(Article)
Subject:
Multimedia Processor
,
Post-Video Processing
Author:
Takashi
Hashimoto
Hisayoshi
Matsuoka
page:
1574
-
1581
-
(Article)
Subject:
Flash Adc
,
Analog System
Author:
Geoff
Jackson
Saleel V
Awsare
page:
1582
-
1589
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